Google Off Campus Drive for Silicon IP RTL Design Engineer, Google Cloud in Bangalore

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
• 1 year of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
• Experience in micro-architecture and design of IPs and subsystems
• Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)

Preffered Qualification's:

• Experience with scripting languages (e.g., Python or Perl)
• Experience in SoC designs and integration flows
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies
• Knowledge of high performance and low power design techniques